Hardware Design

High Level Design Decisions

TAP Radio Interface
As mentioned above, the TAP's baseband algorithms are still being developed. Dedicated baseband processors are available for a wide variety of wireless networking standards, but such devices are not suitable for implementing the custom algorithms in a TAP. The device that provides the baseband processing must therefore be very flexible. Further, these baseband algorithms are expected to be very complex, requiring significant processing resources. The baseband processor must be tailored to the DSP-intensive operations, such as filtering and correlation, which are common in communications algorithms. Finally, the processor must be capable of highly parallel operation in order to realize the bandwidth and throughput goals for a TAP.

Next, the TAP baseband processor connects to multiple radios, each of which communicates via wideband analog interface. Once digitized, each analog interface will require a high throughput, high precision digital connection to the baseband processor. Assume that a TAP's baseband processor controls four radios and that each radio has a analog complex baseband interface (e.g. separate I/Q analog signals) with a bandwidth of 20MHz. This requires the baseband be capable of transferring 320MB/sec in each direction without interruption. This requirement increases even further if the radios used in a TAP have intermediate frequency analog interfaces.

tap board
TAP Wireless Interface Board
It became clear very early in the design process that FPGAs were the only devices which could practically meet all of these requirements. Large FPGAs provide tremendous amounts of processing power, all of which, by definition, operates in parallel. All of an FPGAs interfaces to external devices also operate in parallel, significantly easing the aggregate throughput requirement discussed above. FPGAs are also extremely well suited for DSP-intensive operations. For example, large devices include more than 300 dedicated multiplier blocks, all of which can be used simultaneously.

Once FPGAs were chosen as the TAP's baseband processor, a radio had to be selected. Two options were considered here. First, it would be possible to design a radio from discrete components, implementing all of the necessary mixing, filtering and amplification in a custom circuit. Such a design would provide a completely generic analog interface and could be tailored to the desired bandwidth and radio frequency specifications. Unfortunately, the design of such a system is a very challenging undertaking which falls well outside the expertise of anyone involved with this project. Instead, a third-party radio transceiver was identified which meets most of the TAP radio requirements. This approach significantly increases the probability the the first revision of TAP hardware will work, though a custom radio design is certainly a possibility for later revisions.

wired board
TAP Controller Board
A final high-level design decision involves the partitioning of a TAP into multiple boards. A TAP will have a minimum of three air interfaces, each equipped with four radios. Some TAPs will also have wired network connections in addition to their wireless interfaces. Assuming a baseband processor can handle a single air interface, a TAP will consist of at least three large FPGAs plus 12 radios. Designing a single board with all of these components would be risky and very expensive. Instead, the TAP's functionality is divided across three boards. The first is a simple radio board, containing a single RF transceiver and the necessary analog-digital conversion. The second board hosts the large baseband FPGA and has slots for four radio boards. This board provides the TAP with a single air interface. Finally, a third board contains a smaller FPGA with a wired network interface. This division of hardware seems natural but poses the significant problem of designing some means to interconnect the boards. The wireless interfaces in a TAP will need to communicate with both the wired and other wireless interfaces. Given the very high data rates these interfaces are expected to support, this board-to-board communication must be very fast and have very low latency. Further, an average TAP will consist of four boards, each of which must be able to communicate with every other. If even more boards are added to a TAP (e.g. should additional wireless interfaces be required), this problem of interconnection only becomes more complicated.

Full Tap
Assembled TAP

The solution which was selected for this design is, in many ways, the exact opposite of the bus architecture described above. Instead of having a connections to a common backplane, every board in a TAP is directly connected to every other. This point-to-point topology enables communication between any pair of boards regardless of what resources any other boards are consuming. A fully-interconnected design, however, somewhat complicates the architecture of a TAP. Each board must be equipped with a dedicated connection for every other board in a TAP. Adding a new wireless interface, for example, would consume an additional connection on every existing board. At first a glance, it seems problematic that the resource requirements increase with the number of boards in a TAP. However, if each board could be efficiently equipped with a large number of identical, high speed connections, this architecture is justified. Fortunately, this requirement is easily met in the TAP design, as detailed in the discussion of component selection below.

Low Level Design

This section discusses the choice of parts which seek to fill the roles specified by the high level design described above. The actual design includes a large number of parts, including analog converters, memory and power regulators. Rather than describe all of these parts here, the reader is refered to the schematics for the various TAP boards. Instead, the choice of the baseband FPGA and radio transceiver will be discussed, the two most critical components in a TAP.

The choice of the FPGA for baseband processing is actually fairly straightforward. As described above, this design must provide sufficient resources to implement baseband algorithms which, though not yet defined, are expected to be very complex. As a result, the chosen FPGA should be as large as is reasonably possible. The most advanced FPGAs currently available are those in Xilinx's Virtex-II Pro line. The part chosen for the TAP baseband processor is the XC2VP70, one of the largest parts in the Virtex-II Pro family.

In addition to providing generous logic resources, the Virtex-II Pro baseband FPGA includes a number of additional features which will be critical in the operation of a TAP. The first is the inclusion of multiple PowerPC cores embedded in the logic of the FPGA. These cores are full RISC processors whose external interfaces are tied to the device's programmable logic fabric. The TAP baseband FPGA has two such cores which operate independently. These cores are meant to compliment the operation of the FPGA by providing a means to execute pre-existing software code or to perform other processing which is not well suited for implementation in general logic. It is even possible to run a full operating system in one of the processor cores. Xilinx provides a version of Linux which will boot in the embedded PowerPC and can interact with the custom design implemented in the surrounding logic. This offers the interesting possibility of a TAP being, in essence, a PC with many wireless network interfaces. This abstraction could prove very useful when it comes time to implement higher-layer protocols (MAC, routing, etc) in a TAP.

Another feature of Virtex-II Pro FPGAs key to the TAP architecture is RocketIO, Xilinx's marketing name for their high-speed serial transceiver technology. These transceivers, generically known as MGTs (multi-gigabit transceivers), enable very high throughput, full duplex connections for chip-to-chip or board-to-board communication. Each transceiver is capable of communicating at 3.25Gb/sec, or 406.25MB/sec, over a four wire serial link. Multiple transceivers can be bonded together to achieve even faster aggregate throughput. The TAP baseband FPGA is equipped with 16 such transceivers, providing significant resources for off-chip communications. Eight MGTs are wired to off-board connectors on the wireless interface board, allowing up to eight boards to be fully interconnected when constructing a TAP.

Table 1 summarizes the resources provided by the TAP baseband FPGA. It also lists the resources for a slightly less capable chip, the XC2VP50. This FPGA is pin-compatible with the larger chip and, depending on availability (i.e Xilinx's willingness to donate), may be used in early builds of the TAP hardware.

User I/O 852 996
Gates 5 million 7 million
On-chip RAM 4.2Mb 5.9Mb
18x18 Multipliers 232 328
PowerPC Cores 2
Rocket I/O 16
Price Each $1600 $2500
Table 1: FPGA Resources

A radio transceiver suitable for use in this design proved to be, by far, the most difficult part to choose. The difficulty stems from the scarcity of wideband radio chips which are not tied to a particular baseband processor. A vast majority of wireless networking designs are built to comply with one or more of the IEEE 802.11 standards. A TAP's wireless interfaces, on the other hand, will not use these standards and must be designed to support a multiple antenna physical layer which is not yet defined.

Fortunately, a suitable radio chip was recently released which meets most of the expected requirements for the TAP physical layer. This radio, the MAX2825 from Maxim Integrated Products, operates in the 2.4GHz ISM band and is intended for 802.11b/g products. Its design, however, is fairly generic and will translate any 20MHz bandwidth signal between baseband and any RF between 2.4 and 2.5GHz. The radio's interface truly operates at baseband, consisting of separate complex analog transmit and receive signals with 20MHz bandwidths centered at DC.

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